The present invention relates to stacked microelectronic assemblies and methods of making such assemblies, to methods of forming such assemblies and to components useful in such assemblies.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip is mounted in a package, which in turn is mounted on a circuit panel, such as a printed circuit board, and which connects the contacts of the chip to conductors on the circuit panel. In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. As used in this disclosure, with reference to a flat chip having a front face, the “area of the chip” should be understood as referring to the area of the front face. In “flip-chip” designs, the front face of the chip confronts the face of the circuit panel, and the contacts on the chip are bonded directly to the circuit panel by solder balls or other connecting elements. The “flip-chip” design provides a relatively compact planar arrangement; each chip occupies an area of the circuit panel equal to or slightly larger than the area of the chip front face. However, this approach suffers from cost and reliability problems. As disclosed, for example, in certain embodiments of commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; and 5,679,977, the disclosures of which are incorporated herein by reference, certain innovative mounting techniques offer compactness approaching or equal to that of conventional flip-chip bonding without the reliability and testing problems commonly encountered in that approach. A package which can accommodate a single chip in an area of the circuit panel equal to or slightly larger than the area of the chip itself is commonly referred to as a “chip-size package.”
Various proposals have been advanced for providing multiple chips in a single package or module. In a conventional “multi-chip module,” the chips are mounted side-by-side on a single package substrate, which in turn can be mounted to the circuit panel. This approach offers only limited reduction in the aggregate area of the circuit panel occupied by the chips. The aggregate area is still greater than the total surface area of the individual chips in the module. It has also been proposed to package multiple chips in a “stacked” arrangement, i.e., an arrangement where chips are placed one on top of another. In a stacked arrangement, several chips can be mounted in an area of the circuit panel that is less than the total area of the chips. Certain stacked chip arrangements are disclosed, for example, in certain embodiments of the aforementioned '977 and '265 patents and in U.S. Pat. No. 5,347,159, the disclosure of which is incorporated herein by reference. U.S. Pat. No. 4,941,033, also incorporated herein by reference, discloses an arrangement in which chips are stacked one on top of another and interconnected with one another by conductors on so-called “wiring films” associated with the chips.
Another approach is presented in commonly assigned U.S. Pat. Nos. 6,121,676 and 6,225,688 and U.S. patent application Ser. No. 09/776,356 filed Feb. 2, 2001, the disclosures of which are incorporated herein by reference. Certain preferred embodiments of the stacked microelectronic assemblies disclosed in these patents and application include an elongated, tape-like flexible substrate having terminals for connection to an external circuit and having a plurality of chips distributed along the axis of elongation of the substrate and attached thereto. The flexible substrate is folded so as to stack the chips in substantially vertical alignment with one another. While assemblies according to these embodiments provide useful improvements, still further improvements would be desirable. In these assemblies, the individual chips are connected to the terminals and to each other by traces extending generally lengthwise along the elongated substrate. The lengths of the traces connecting the various chips to the terminals may differ from one another. Thus, the chip furthest from the terminals along the length of the substrate is connected to the terminals by relatively long traces, whereas the chip closest to the terminals is connected to the terminals by shorter traces. As the delay in signal propagation along the traces varies with the length of the traces, such delays increase as the number of chips distributed along the axis of the flexible substrate is increased.
Certain preferred embodiments of U.S. Pat. No. 5,861,666, the disclosure of which is incorporated herein by reference, disclose an assembly of plural chip-bearing units vertically stacked one atop another. Each unit includes a small panel or “interposer” and a semiconductor chip mounted thereto. The units are stacked so that the chips overlie one another and are electrically interconnected with one another, for example, by solder balls connecting conductive features of adjacent interposers to one another. Assemblies of this type provide rapid signal propagation to all of the chips in the stack. However, the number of electrical interconnections increases as the number of chips in the stack is increased.
Thus, still further improvements in stacked chip assemblies would be desirable.
Indeed, a growing number of portable devices, such as cellular phones and personal digital assistants (PDAs), are becoming more and more “PC-like.” These portable devices have a microprocessor and memory for storage of programs and data, are typically small in size, and have low power requirements. As such, the above-mentioned stacked chip assembly is a useful integrated circuit (IC) package for use in such an environment since a stacked chip assembly can incorporate a number of functions in a small footprint with low power dissipation. For example, a folded stack package may incorporate a microprocessor device and one or more memory devices (e.g., static random access memory (SRAM) and lash memory).
Unfortunately, in manufacturing a multiple die package, such as a folded stack package, the package yield from a manufacturing “burn-in” test may be low. For example, if just one of the devices in a folded stack package fails during the burn-in test—either the entire folded stack package is scraped or must be re-worked, i.e., any devices that fail are replaced. However, such identification and replacement of failed devices adds time and labor to the burn-in process.
Thus, still further improvements in testing of stacked chip assemblies would also be desirable.